1. Field of the Invention
The invention relates generally to a method of fabricating semiconductor devices and, more particularly, to a method forming a micro pattern in a semiconductor device, in which spaces between lines are formed differently and critical dimension (CD) can be controlled.
2. Discussion of Related Art
Exposure for the preparation of a 70 nm pattern size in semiconductor devices is conventionally performed using ArF exposure equipment. However, in order to form a pattern size of 50 nm or less, a method of forming a micro pattern through dual exposure etch has been proposed. However, the method cannot be applied to the process because it cannot control the overlay, which is the most important variable in the dual exposure.
The dual exposure will be described below with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, exposure and development processes are firstly performed to form a photoresist pattern. A to-be etched layer that has first been exposed using the photoresist pattern as a mask is etched to form first line patterns 10 and first spaces 20. Each of the first line patterns 10 has a width of 100 nm and each of the first spaces 20 has a width of 100 nm.
Referring to FIG. 1B, exposure and development processes are then again performed to form a second photoresist pattern. The to-be etched layer that has been exposed a second time is etched to form second line patterns 30 and second spaces 40. Each of the second line patterns 30 has a width of 50 nm and each of the second spaces 40 has a width of 150 nm.
However, where after the pattern is first etched, exposure is performed a second time by aligning the overlay using an alignment key, the alignment key must be moved 50 nm to result in the pattern spacing shown in FIG. 1B. It is, however, difficult in practical terms to control the overlay accuracy of the exposure equipment to 10 nm or less.
In other words, in an ideal case, where a line pattern of 50 nm and a space of 150 nm are to be obtained, if misalignment occurs to the left side, a pattern width of 60 nm and a space of 140 nm are secured as shown in FIG. 2A. That is, a pattern of 50 nm or more is formed. On the other hand, if misalignment occurs to the right side, a pattern width of 40 nm and a space of 160 nm are secured as shown in FIG. 2B. Accordingly, it is possible to firm a pattern, but is impossible to control CD in terms of the process.
Furthermore, a method of forming a pattern having a pitch smaller than the resolution of the exposure equipment includes a pattern formation method employing double exposure technology (DET) or a spacer. However, with DET, it is difficult to overcome CD failure incurred by misalignment and this is not practical in actual device fabrication. Furthermore, in a pattern formation method employing the spacer, it is very difficult to connect the cell and the peri region and also difficult to form the lines and spaces of the cell differently. Accordingly, the pattern formation method employing the spacer is difficult to apply to actual device fabrication.